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Altera_Forum
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14 years ago

EMP1270 BGA burning up

On a new design we have a repeated problem that the EMP1270 developes a short between pwr and gnd and smokes. Single 3.3v supply operation, all other devices on board on same supply. The only exposed CPLD pins are Jtag and some GPIO's for debug, we have anti static ESD foam across all pins on the headers.

The problem only happens on power up, once board is up, no problems.

We suspect either ESD or some random overshoot of the 3.3V, using a switcher regulator, LM2678. watching a scope, didn't see any overshoot for dozens of power up cycles.

Any other theories are welcome. this has happened on different board designs, boards assembled by different places.

Can/will Altera perform an analysis on blown part?

Does the symptoms, pwr gnd short, point to one theory or the other?

I assume the CPLD would be most sensitive to supply overshoot due to it's 2.5V capability, indicating thinner gate oxide than a pure 3.3V part?

ideas and thoughts welcome

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Have you replaced the CPLD in a failed board, to see if it is systematic with the board?

  • Altera_Forum's avatar
    Altera_Forum
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    What type of design logic have you implemented in the CPLD?

    Back before I knew better, I created a design that used a latch, rather than a register. I placed-and-routed the design with Mentor LeonardoSpectrum and then WYSIWYG compiled the EDIF netlist with MAX+Plus II. I downloaded the design into a FLEX10K, and very soon after I could smell something cooking ... the FLEX10K device!

    I ran the post-P&R design in Modelsim to try and determine the problem. Modelsim showed an oscillation of a signal associated with the latch. The placement of the latch was such that there were different delays in the latch feedback paths. Those delays created an oscillator at several hundred MHz (actually several oscillators, since the latch was multi-bits). This was enough to cook the chip.

    If you are seeing a random issue across boards, then perhaps you have something that is design related, and the slight differences in device timings causes the problem to occur on only some boards.

    Replace the device on a bad board with a blank CPLD. If that CPLD does not destroy itself after the board has been powered up for longer than it took for the first CPLD to be destroyed, then I would look at the design, eg. simulate the post-P&R design.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    Even if the thread is inactive for a year ...

    I have a very similar problem with our boards.

    We are using the same device and package,

    Sometimes when switching on the CPLD gets burned immediately

    and the 3.3.V power rail has a shortcut.

    Getting the CPLD off from the PCB, I could verify that at least in one

    case VCCINT had a shortcut (below 5 Ohms) while VCCIO was ok.

    The power supply is realized using a linear regulator 5V -> 3.3V.

    5V are generated by a switching regulator.

    Could you figure out the reason for the failure on your boards ?