New Contributor
New ContributorHi I even managed to run emif toolkit on my custom board. One DDR controller at a time. It seems daisy chaining was the issue. I will debug it later and I will try Quartus 19.4. For the time being I have problem with interpretation of my first failing calibration reports. Calibration failed at last stage 4 according to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf page 478. Why read and write margins are set to 0? Moreover PAR_IN is uncalibrated, how could it reache stage 4 without PAR_IN working? Shouldn't it report failure at stage 1? Please see comparison with identical slot and sodimm where PAR_IN and ADD_14-16 are calibrated.
