Tried toolkit restart, machine reboot, FPGA reprogram - nothing helped.
I also encountered new error:
link_project_to_device -device_name {10AX115H1(.|E2|ES)|10AX115H2|..@1#1-2} -hardware_name {USB-Blaster on localhost (1-2)} -sof_file {/home/slawek/sofs/sdnbox_pcb_tester_ddr3.sof}
Linking device 10AX115H1(.|E2|ES)|10AX115H2|..@1#1-2 on hardware USB-Blaster on localhost (1-2) using .sof file /home/slawek/sofs/sdnbox_pcb_tester_ddr3.sof.
Error occurred while running the System Console command design_load {/home/slawek/sofs/sdnbox_pcb_tester_ddr3.sof}. System Console returned the result java.util.concurrent.ExecutionException: java.lang.Exception: Filesystem is not ready
invoked from within
"design_load /home/slawek/sofs/sdnbox_pcb_tester_ddr3.sof
"
invoked from within
"interp eval $slave {
design_load /home/slawek/sofs/sdnbox_pcb_tester_ddr3.sof
}". You must shutdown the toolkit and restart.
File system is not ready exception seems like toolkit internal error? I'm running on SMP Debian 4.19.98-1. I can try on Ubuntu 18.04 if it might help.
Indeed JTAG connection might be unstable, but Transceiver Toolkit was working fine. I'm already using 6M as Terasic programmer does not support higher frequency (changing frequency neither). I will try to run EMIF toolkit on Terasic eval board to isolate problem.
Please find below output from jtagconfig -d:
slawek@sdnbox-3:~$ jtagconfig -d
1) USB-Blaster [1-2]
(JTAG Server Version 19.3.0 Build 222 09/23/2019 SC Pro Edition)
02E660DD 10AX115H1(.|E2|ES)/10AX115H2/.. (IR=10)
Design hash 0720A09D3DA446F22D79
+ Node 0C206E00 JTAG PHY #0
+ Node 0C206E01 JTAG PHY #1
Captured DR after reset = (02E660DD) [32]
Captured IR after reset = (155) [10]
Captured Bypass after reset = (0) [1]
Captured Bypass chain = (0) [1]
JTAG clock speed 6 MHz
Can I have both Transceiver toolkit and Emif toolkit active in the same sof? Or this might be source of problems?
EDIT: Ubuntu 18 also reports Filesystem is not ready exception.