emif avalon handshake signals are unstable.

Problem resolved, driver error.

I created my own model for the memory controller and used it to verify the logic that drives the memory controller.

I am using modelsim to verify my design which means I cant use the Avalon bus monitor to verify the correct behavior of the design because it uses features that are not supported by Modelsim.

Which meant I was verifying a bus driver I designed with a model I designed.

Not the way to go.

My logic expected an active high avs_wait_request but QSYS generated a memory controller with a active low avs_wait_request_n port.

But the design worked so I didn't think to investigate further.

What is happening is that the memory controller accepts multiple read commands because the avs_read signal is kept high, but eventually cant accept anymore and drives the avs_wait_request_n port low.

It will perform a read cycle to the DDR module for each read command it receives.

This explains the multiple avs_readdatavalid pulses.

The data is the same for all, so it doesn't toggle.