Effect of nCE (Chip Enable)

Hi,

The nCE is active low chip enable which enables FPGA. The nCE needs to be low all the time from power up until under mode.

It is not that recommended for the nCE cannot be high in user mode. If the nCE is high (regardless during configuration or user mode), the FPGA will not be able to function correctly.

For example, if nCE high the JTAG will not work. Most likely the design and IO pins will not work correctly even though the FPGA has been configured.

You can check any FPGA pin connection guideline mentioned:

When the nCE pin is low, the device is enabled. When the nCE pin is high, the device is disabled.

https://www.altera.com/documentation/lit-dpcg.html

When the nCE is high causing to disable the device, there is no reason for pulling the nCE high at any time. There is no timing since the nCE should be low all the time.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)