]I usually don't find the RTL view very user readable ;) I mostly use it to check that the synthesizer understood the code the way I wanted it to.
As for the graphical input, it is true that it looks easier when you start making FPGA designs. But after a while, you have some needs that are difficult to cover with bdfs:
- Big projects: in my company we have some old complex projects done entirely in bdf. It spawns on a couple dozen pages, filled with gates, registers, comparators, arithmetic operators... It is very difficult to follow the original author's intentions
- Comments: it is difficult to comment a graphical file. For a complex project, lack of good comments is asking for trouble on the long run
- Maintainability: when adding a new functionality, you may have to move half of the components around the screen to make space for your new components. Also as you discovered, adding/removing ports can also take a while
- Reusability: with a bit of experience, you can write generic HDL code that uses configuration parameters, and that can be reused in several projects and cope with different needs/situations. Big time saver in the long run
- Source control: I never tried to use CVS/SVN with bdl files, but text files are always easier to put under source control.
I think al those are good arguments in favor or HDL files. Of course you need to learn it, but once you are used to it, it is faster than using graphical input, and you'll always gain on the long term.
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