Edge-aligned center aligned DDR Timing constrains

.sdc I assume? What you have is not really edge-aligned or center-aligned(although probably closest to edge-aligned). It not symmetric around either edge though.

create_clock -name ext_ssync_clk -period 20.0

set_input_delay -max 3.5 -clock ext_ssync_clk [get_ports {din[*]}]

set_input_delay -min 3.5 -clock ext_ssync_clk [get_ports {din[*]}]

set_input_delay -max 3.5 -clock ext_ssync_clk [get_ports {din[*]}] -clock_fall -add_delay

set_input_delay -min 3.5 -clock ext_ssync_clk [get_ports {din[*]}] -clcok_fall -add_delay

I'm ignoring any board skew, but this describes what is going on outside the device. Now let's say you have a clock coming into the FPGA:

create_clock -period 20.0 -name fpga_clk [get_ports fpga_clk]

The setup relationship will be 10ns for opposite edge transfers and hold will be 0ns for same edge, which will be the most restrictive. TimeQuest will basically evaluate that your data delay can't be 10-3.5=6.5ns longer than your clock path or you'll have a setup violation, and it can't be 0ns or less(more negative) than your clock path inside the FPGA or you will have a hold violation. The problem is that your data path will be short since it directly feeds the pin while the clock path is long, so you'll probably fail hold. (The fitter could crank up the input delay chain and possibly get it to work)

Now let's say you add a PLL in source-synchronous compensation mode. You will get identical analysis except your clock path will be shorter since it will be compensated for by the PLL. The fitter might still turn up the IO delay chain if there is one, but this might work.

Now let's say you phase-shift the PLL output 90 degrees. This results in a 5ns setup relationship and -5ns hold relationship. Your data path can't be more than 5-3.5=1.5ns longer than the clock path inside the FPGA, and can't be less than -5ns shorter than the clock path. In other words, your data can be +1.5 to -5ns delay compared the clock path. (This makes since since the data period is 10ns. This allows for 6.5ns of it to be chewed up inside the FPGA, as 3.5ns of it was chewed up outside the FPGA.) This is probably the best layout since having the clock and data pretty closely match will meet timing. You could tweak the PLL phase-shift a bit but not sure it will help).

(Been a while since I've analyzed these and typing from memory, but I think that's correct...)

The following might help but is often overkill:

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest