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mikefr's avatar
mikefr
Icon for New Contributor rankNew Contributor
1 year ago

E-tile and F-tile 64b/67b encoding

Hi,

I want to do SFPDP gen3 with Agilex 7 so I need 64b/67b encoding.

In 683458 "Agilex™ 7 FPGAs and SoCs Device Overview" it is written that PCS of e-tile supports 64b/67b encoding.

I looked in 683723 "E-Tile Transceiver PHY User Guide" but I could not find any information how to configure the IP to use this encoding so how to do this?

For F-tile in "Agilex™ 7 FPGAs and SoCs Device Overview" there is nothing about supported encoding but I found the "F-Tile Interlaken Intel® FPGA IP User Guide" in which encoding is done in FPGA logic so I guess that for F-tile it has be done like this?

Regards

Mike

Other Ips

4 Replies

  • Harshx's avatar
    Harshx
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

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  • mikefr's avatar
    mikefr
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hello,

    I have contacted my FAE about this and he told me that it is a mistake in the document, E-tile doesn't support 64b/67b in PCS.

    It is like the F-tile for 64b/67b it has to be done in FPGA logic.

    Unfortunately there is no example design for this.

    Regards

    Mike

  • Harshx's avatar
    Harshx
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi,

    Thank you for your information. I hope it'll be updated soon.

    I'm closing the incident.

    Regards,

    Harsh M