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Altera_Forum's avatar
Altera_Forum
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10 years ago

Dynamic adjustment of Cyclone III IOE Programmable Delay?

Hi, is it possible to adjust the Cyclone III IOE delay at runtime, or only at bitstream generation time?

In particular, the i/o buffer megafunction (altiobuf) user guide (http://application-notes.digchip.com/038/38-21601.pdf) for StratixIII+CycloneIII says that it is possible, but all the examples use the StratixIII-specific StratixII_CONFIG_IO primitive, which doesn't work on CycloneIII (or is there some trick that makes it work?).

According to the Cyclone III datasheet the input-pin-to-register and output-register-to-pin delay lines have a range of 0ps to 1000ps or more, but I need to be able to adjust this on a per-board and per-pin basis, so the values aren't known at the time the bitstream is written. I need to be able to sweep the values while checking error rates, similar to how the PLL output phases can be adjusted in real time.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    Seems like there is no further description. It would be great if you could further elaborate on your inquiry
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    The forum has done something very strange and deleted my post but didn't delete the thread! Here is what I wrote:

    Sorry for the double-post, but the forum is doing really strange stuff with my threads. The previous thread I started has zero postings (not even my own!). Did a moderator delete my post but not delete the thread? Sorry if I did something wrong...

    Anyways:

    Is it possible to adjust the Cyclone III IOE delay at runtime, or only at bitstream generation time?

    In particular, the I/O Buffer Megafunction (ALTIOBUF) User Guide for StratixIII+CycloneIII says that it is possible, but all the examples use the StratixIII-specific StratixII_CONFIG_IO primitive, which doesn't work on CycloneIII (or is there some trick that makes it work?).

    According to the Cyclone III datasheet the input-pin-to-register and output-register-to-pin delay lines have a range of 0ps to 1000ps or more, but I need to be able to adjust this on a per-board and per-pin basis, so the values aren't known at the time the bitstream is written. I need to be able to sweep the values while checking error rates, similar to how the PLL output phases can be adjusted in real time.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Sorry about the double-post above. I tried to delete the duplicate but the forum barfed at me:

    Fatal error: Existing data passed is not an array

    Called set_existing in [path]/editpost.php on line 1324

    in [path]/includes/class_dm.php on line 265

    Sad forum :(
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    As I mentioned in your other post - the buffer dynamic delay chain is not available in the ALTIOBUF for Cyclone III. So, it cannot be dynamically changed. It can only be modified prior to bitstream generation.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    As I mentioned in your other post

    --- Quote End ---

    My other post?

    --- Quote Start ---

    the buffer dynamic delay chain is not available in the ALTIOBUF for Cyclone III. So, it cannot be dynamically changed. It can only be modified prior to bitstream generation.

    --- Quote End ---

    Ah, that is unfortunate. Thanks for clarifying.

    Cheers,

    Alex

    --- Quote End ---