Dynamic adjustment of Cyclone III IOE Programmable Delay?

Hello,

According to the Cyclone III Device Handbook, Volume 2, Tables 1-37 and 1-38, dated July 2012, this device has a programmable delay element on both inputs and outputs. On a C8 grade device the input-pin-to-input-register delay ranges from 0..2300ps and the output-register-to-output-pin offset ranges from 0..1107ps. If the settings are known at bitstream-generation time they can be configured in the QSF tool (and probably other ways too).

However I need to adjust these values at runtime, in the field, on a board-by-board basis, to compensate for board-specific delays. Much like the PLL dynamic reconfiguration.

The "i/o buffer megafunction (altiobuf) user guide (http://application-notes.digchip.com/038/38-21601.pdf)" version 1.0 dated November 2007 states (page 1-1) that it describes the IO buffers of the Cyclone III and Stratix III devices and (further down the same page) that "Dynamic delay chains are integrated in the input path for the input and bidirectional buffers.". However all of the examples in the document are for Stratix III, not Cyclone III, and all of them require the STRATIXIII_IO_CONFIG primitive which, obviously, is not available on Cyclone III.

Where can I find instructions on how to dynamically reconfigure the IO delay setting for Cyclone III?

Thanks!

PS, I don't use the Quartus GUI, so advice in terms of the fundamental primitives (QSF files, Verilog, etc) are more helpful.