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ZBrig
New Contributor
New ContributorDuplicating memory writes along the PCIe bus
I am attempting to monitor all writes to system RAM with the aim of detecting malicious programs, using a independent co-processor. To prototype this I will be using an Intel Stratix 10 GX FPGA conne...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi,
In this case, the FPGA is the PCIe endpoint, so the communication between onboard RAM is with the PCIe endpoint. I don't see this is possible to use the onboard RAM as the main system memory that requires to work with root port (host CPU).
I have not too sure about your requirement, but you may refer to the PCIe DMA design example, which allows you to move data back and forth between PCIe domain and the local domain (application). There is a descriptor that you need to configure the source address, destination address, and size.
Regards -SK
