Forum Discussion

TimSch's avatar
TimSch
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Dump sdram content to file De10-lite (MAX 10 10M50DAF484C7G)

Hello!

Like the guy a few years ago in this post, I need to dump the content of my sdram to my PC.

I need to debug an vhdl application with ~2.52Mbit data. Too much for signal tap.
Unfortunately all the links in the answer are dead and I have still no clue.

What's the easiest way to access contents of the ram and dump them into a file to process them on the computer?

I'm using a DE10-lite board (MAX 10 10M50DAF484C7G).

All GPIO Ports are blocked by a TRDB_D5M camera. I could try to use the not connected pins but a solution using the USB Port would be great.

Thanks in advance

Tim

Generic Io
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    2 years ago

    Hi Tim,


    The SDRAM NIOS test is a close example for your application to communicate the FPGA to PC through a JTAG connection or using USB Blaster.

    Maybe you can check the example design and make modification on it.


    Regards,

    Adzim


5 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Tim,


    Do you still need help on this thread?

    I saw you have posted SDRAM related issue in other thread.

    Just wondering if you still need help on this thread.


    Regards,

    Adzim


    • TimSch's avatar
      TimSch
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hello Adzim,

      this is more kind of a general question *after* I got over my struggles with SDRAM in general.

      So yes, this question still relevant for me. It's not about validating a written value, it's about validating (many) calculations and such.

      The calculations are done by the FPGA and the validation or maybe further processing should be done on NIOS (or at first the PC).

      Thanks

      Tim

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Tim,


    The SDRAM NIOS test is a close example for your application to communicate the FPGA to PC through a JTAG connection or using USB Blaster.

    Maybe you can check the example design and make modification on it.


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


  • TimSch's avatar
    TimSch
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hello Adzim,

    thanks for your input. The NIOS idea is a very good one. I already discovered the files, but - why ever - I didn't considered it as possible solution for me.

    I will look into that.