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TimSch's avatar
TimSch
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2 years ago
Solved

Dump sdram content to file De10-lite (MAX 10 10M50DAF484C7G)

Hello! Like the guy a few years ago in this post, I need to dump the content of my sdram to my PC. I need to debug an vhdl application with ~2.52Mbit data. Too much for signal tap. Unfortunately a...
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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    2 years ago

    Hi Tim,


    The SDRAM NIOS test is a close example for your application to communicate the FPGA to PC through a JTAG connection or using USB Blaster.

    Maybe you can check the example design and make modification on it.


    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Tim,


Do you still need help on this thread?

I saw you have posted SDRAM related issue in other thread.

Just wondering if you still need help on this thread.


Regards,

Adzim


  • TimSch's avatar
    TimSch
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hello Adzim,

    this is more kind of a general question *after* I got over my struggles with SDRAM in general.

    So yes, this question still relevant for me. It's not about validating a written value, it's about validating (many) calculations and such.

    The calculations are done by the FPGA and the validation or maybe further processing should be done on NIOS (or at first the PC).

    Thanks

    Tim