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Altera_Forum
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14 years ago

Dual Port Ram problems : Synthesizes error with one or two clock signals

Hello, I was running in a problem and can't find a way out . Although there are already a lot of posts concerning problems with dual port rams, I couldn't found a solution. I am using a DE1 boa...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hello,

you have provided the same info to use the Statement: set_parameter -name CYCLONEII_SAFE_WRITE VERIFIED_SAFE. It does not solve the dual-clock problem. I still receive the message : Error: M4K memory block WYSIWYG primitive "lpm_ram_dp0:inst4|altsyncram:altsyncram_component|altsyncram_1o12:auto_generated|ram_block1a16" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature. If I use my design, I will get sythesizes errors. Seems to be , on my DE1 board is an old version of chip installed.

Anyway, I have a workaround.