Dual Port Ram problems : Synthesizes error with one or two clock signals

It's always instructive to read the Quartus error message completely:

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Error: M4K memory block WYSIWYG primitive "altsyncram:altsyncram_component|altsyncram_fv42:auto_generated|ram_block1a27" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.

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The interesting point is the reference to Cyclone II errata sheet. Cyclone II early revisions had a silicon bug that is handled by a workaround in Quartus, unfortunately doubling memory resource consumption for single port and not working with true dual port RAM at all.

Presuming you have EP2C20 Revison B chips, all you have to do is to add a synthesis parameter to your design settings. Use the below tcl line or enter it under default parameters. You should also refer to the Cycclone II errata sheet to learn more about the issue.

set_parameter -name CYCLONEII_SAFE_WRITE VERIFIED_SAFE

You can implement 13000 words DP RAM in your device using this settings.

Regards,

Frank