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Altera_Forum
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14 years ago

Dual Port Ram problems : Synthesizes error with one or two clock signals

Hello, I was running in a problem and can't find a way out . Although there are already a lot of posts concerning problems with dual port rams, I couldn't found a solution. I am using a DE1 boa...
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Altera_Forum
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14 years ago

I simply went to megawizard, chose dual port ram, used 16 bits width x 6200 and set to single clock.

Here are some info on my compilation:

Quartus II Version 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition

Revision Name test

Top-level Entity Name test

Family Cyclone II

Device EP2C20F484C7

Timing Models Final

Met timing requirements Yes

Total logic elements 38 / 18,752 ( < 1 % )

Total registers 4

Total pins 93 / 315 ( 30 % )

Total virtual pins 0

Total memory bits 99,200 / 239,616 ( 41 % )