Dual Port Ram problems : Synthesizes error with one or two clock signals

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I reproduced this problem. It says this feature of dual clock dual port is not supported in current device and current software.

Then I tried single clock and it was successful and used 32 blocks of M4ks.

Thus you may need to use one clock plus a dc fifo

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Thank you for your reply.

I am not passed with my single clock dual port implementation.

May you provide me plaese a working dual port ram code or do

you have plaese a note for me, why my code is not working