Dual DDR connection to Agilex 5

Hi Adzim

We think we meet the HPS-EMIF restrictions described in the EMIF user guide. There are only not so clear the following restrictions:

• Reference clock sharing is not allowed between HPS-EMIF IP and other IPs.
  • There are only the next parameters configurable from the platform designer for HPS-EMIF, DDRAM width, and DDRAM type (DDR4/LPDDR4/..). We see in the top file of the project that two different REF_CLK signals are used, and these signals are reserved only for specific EMIFs, not for other IPs.
• For multi-channel EMIFs or when multiple EMIFs are used inside HPS-EMIF IP, they must have identical IP parameters.
  • Again, only the next parameters are configurable by the platform designer for HPS-EMIF, DDRAM width, and DDRAM type (DDR4/LPDDR4/..). Therefore, it is hard to completely confirm that both EMIF IPs (Fabric EMIF, HPS EMIF) use identical parameters.
  • It is unclear to us what multiple EMIFs used inside HPS-EMIF mean.

Again, I repeat our question: Is it possible to use HPS-EMIF and Fabric-EMIF (1x16 LPDDR4) connected to one HSIO bank 3A? If yes, how to configure it? There are no other signals connected to such an HSIO bank

Thanks for any comment, Josef