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Altera_Forum
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11 years ago

DSP Dev Kit PLL Output Pins Question

I have the DSP development kit that has the Cyclone 2. It has SSRAM and some DDR2 memory. I am testing the SSRAM. I have it working at 100 MHz. In the top level code I am using a PLL to generate 3 cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks.

It took a day to get it working at 100 MHz. The trick was to get the correct Cypress data sheet and follow the timing diagrams. Using SignalTap my code writes and reads all locations. You are correct because if jitter was a problem it wouldn't work. Won't worry about it

I'll check Pin Planner.

Swimteam.