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Honored ContributorDriving differential clock from Cyclone III Dev Board to daugther card
Hello, I am attempting to drive a differential clock out of the Cyclone III Development Board (EP3C120F780) to the "Data Conversion HSMC" daughter card. I want to clock data to a 14-bit DAC on...
Altera_ForumHonored Contributor
Honored Contributor@FvM, thanks for the reply. Are you saying that this particular distence rule is improper? In that case, how do I removed it?
Also, I am using ALT_OUTBUF_DIFF to convert from single ended clock from the PLL to differentia outputl. Is there another way to do this? Just using a NOT gate to generate one side of the differential will cause clock skew, would it not?
