Driving differential clock from Cyclone III Dev Board to daugther card

@FvM, thanks for the reply. Are you saying that this particular distence rule is improper? In that case, how do I removed it?

Also, I am using ALT_OUTBUF_DIFF to convert from single ended clock from the PLL to differentia outputl. Is there another way to do this? Just using a NOT gate to generate one side of the differential will cause clock skew, would it not?