Altera_ForumHonored Contributor8 years agoDriving DCLK pin after FPGA configuration Hi, We are using 10CL016 FPGA and configuring it in Passive serial mode from a Host processor. The SPI clock is connected to the DCLK pin of FPGA. We need to use the Host SPI interface eve...Show More
Recent DiscussionsError (209014): CONF_DONE pin failed to go high in device 1.Implementation of lower data rate.eFUSE : Agilex F series and AGilex I series PCIe cardIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAEP4CGX22CF19C8N Failure Short D8 to C8