Driving Cyclone III PLL using general purpose input pin

In cycloneIII handbook it is mentioned that "Clock control blocks that have inputs driven by internal logic are not able to 'drive' PLL inputs".

What exactly they mean by the term 'drive'?

Is it that PLL wont give any output if I use an internal logic driven global clock buffer as an input to the PLL?

Or is it just that PLL won't be able to compensate for the delay of the internal logic but will provide the desired output?

Or is it something else?