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Altera_Forum
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14 years ago

Driving AdressData on the same Bus

Hi, Please can somebody give me any advice how the VHDL Code for driving the A0-A7=D0-D7 with the Latch Register could looks like. I have been trying without success to solve it. I ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

You are talking about the FPGA part to drive the multiplexed bus? Start with sketching a timing diagram.