Driving a module output with a reg?

My way might be a little confusing at first. I typically one-hot encode my statemachines.... and I don't write them as giant case statements either which throws people off who code statemachines the way they learned in school.

The way I code your sort of statemachine would be:

- 3 bit counter (same state encoding)

- counter enable driven by an assign statement that determines when to move to the next state

- bunch of assign statements for all the outputs (or register enables depending on whether those outputs need to be captured by a register

That only works for sequential state machines, for non sequential I typically one-hot encode them and build the state transistion logic manually. If the state machine becomes too big for one-hot encoding... well in my opinion that means you haven't though it through enough and should consider assembling smaller statemachines, and if that doesn't work then you probably have something that belongs in the software realm anyway (so Nios II would be an option).

If you are wondering why I prefer this method it's mainly two reasons: 1) my coding style is to never put blocking operations in an always block, 2) I prefer to code without relying much on synthesis to optimize things for me.