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Altera_Forum's avatar
Altera_Forum
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7 years ago

drive the input pins during the power-up/down sequence

Hi, Can I set the output of the external, peripheral chips(connected to the FPGA Arria10) in the in the VCCIO-GND voltage range during the power-up/down sequence for LVDS Banks? Can I set the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

the table 124 shows:

1. 3VIO banks - Tristate.

Is it necessary to install this mode(Tristate) on the outputs of the external, peripheral chips without pull-up or pull-down resistors?

Is it necessary to install this mode(Tristate) on the outputs of the external, peripheral chips if the VCCIO=1.8V?

2. LVDS I/O banks - Drive to GND or Drive to VCCIO. Why can't these contacts be drived in the VCCIO-GND voltage range?