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Altera_Forum's avatar
Altera_Forum
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7 years ago

drive the input pins during the power-up/down sequence

Hi, Can I set the output of the external, peripheral chips(connected to the FPGA Arria10) in the in the VCCIO-GND voltage range during the power-up/down sequence for LVDS Banks? Can I set the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi,

You can find the information from the "Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook".

Refer Table:124

https://www.altera.com/en_us/pdfs/literature/hb/arria-10/a10_handbook.pdf

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)