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Rkhed's avatar
Rkhed
Icon for New Contributor rankNew Contributor
5 years ago

DRC rules Script issue

Hello, I'm running DRC rules given in below link. https://community.intel.com/t5/FPGA-Wiki/Automated-EMIF-Layout-Checks/ta-p/735221?wapkw=Automated%20EMIF%20Layout%20Checks However, after exec...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

The error comes from the hyperlynx tools instead of Intel FPGA's tools. Thus, you need to contact hyperlynx to get the support.