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Altera_Forum
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7 years ago

DQS Input and Output Timing Constraints

Greetings, I have a DDR controller which has a bidirectional DQS (data strobe) signal. In read states, the DDR device is driving DQS, as well as some data bits which have timing relationship to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

As an experiment, I removed all statements related to input constraints, and just focused on the output constraints: 

create_generated_clock -name CLK_ddr_ldqs_OUTPUT -source { inst5|altpll_component|auto_generated|pll1|clk } 
set CLK_ddr_ldqs_n_OUTL CLK_ddr_ldqs_OUTPUT;
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL $tDS -max 
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL -$tDH -min 
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL $tDS -max  -clock_fall -add_delay
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL -$tDH -min  -clock_fall -add_delay

Now, the timequest looks as I'd expect (attached).

So obviously the SDC needs this "create_generated_clock" statement. To prevent the compiler from complaining, I had to remove the "create_clock" statement from the input portion. Is there a way to keep both? sstrell mentioned not having derive_pll_clocks? What would my constraints need to look like?