What do I do if I have the error "Downloading ELF failed" in Nios II SBT? I built a system in Qsys that had 0 errors, it compiled and I could load it to the board. What is then the error in Nios II SBT when I can't load the ELF file? I tried different run configuration but none of them works. The processor doesn't seem to respond: $ nios2-download -g system.elf Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused

I am suspecting that the Nios didn't manage to boot up (from the message above). Perhaps you can try a simple Nios design that boots from on-chip memory to confirm this.

I get the same error with a simple design. First I had to increase the on-chip memory to 64 K. Now I see Nios doesn't start. Maybe I have some design error. How can I know? $ nios2-download -g /home/developer/proj/quartus0423/software/nios2hello/nios2hello.elf Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused

you have to check those. 1) reset_n do you give reset signal to nios? at least you need to give signal which stuck high. or a pulse it becomes low once is better. 2)JTAG uart. if your Qsys does not have JTAG uart. you have no way to connect with your Qsys. 3) clock. you certainly need clock after all. you need double check if the clock is correct.

Checkout this video and let us know if this helps ... it covers several ways to debug Nios+bare metal systems https://www.youtube.com/watch?v=tkvykoowbfe&t=57s&index=40&list=pl0pu5hg9ynizn8vpd1jrnwk6dlauccmdr

--- Quote Start --- you have to check those. 1) reset_n do you give reset signal to nios? at least you need to give signal which stuck high. or a pulse it becomes low once is better. 2)JTAG uart. if your Qsys does not have JTAG uart. you have no way to connect with your Qsys. 3) clock. you certainly need clock after all. you need double check if the clock is correct. --- Quote End --- I'm not sure if there is something wrong with my Qsys design. You may look from the link http://i.imgur.com/l4vag3w.png It gives no errors in Qsys, it compiles but when I try and run my program it won't start.

Downloading ELF failed | Altera Community

18 Replies

Altera_Forum
Honored Contributor
8 years ago
The design looks like this http://i.imgur.com/z93jrly.png
It compiles. The projects builds. It doesn't work. Fails with "downloading ELF failed".
Altera_Forum
Honored Contributor
8 years ago
Are you running the project after connecting to any DE board. Also after you build the project. Go to quartus compile the project and dump into FPGA. And then comeback to eclipse and select run as hardware.
Altera_Forum
Honored Contributor
8 years ago
Also while you are generating the qsys project. Just have a look in to the files in the pop up where the message appears as generated successfully. Is there nay error or warning as FWD_pointer or something. OR you can go to nios command shell in qsys<tools. Just have a look if this message popups or not.
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Are you running the project after connecting to any DE board. Also after you build the project. Go to quartus compile the project and dump into FPGA. And then comeback to eclipse and select run as hardware.
--- Quote End ---

Yes I connect it to the DE2-115. I do it right. Nothing works.
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Also while you are generating the qsys project. Just have a look in to the files in the pop up where the message appears as generated successfully. Is there nay error or warning as FWD_pointer or something. OR you can go to nios command shell in qsys<tools. Just have a look if this message popups or not.
--- Quote End ---

There is no indication that I'm doing anything wrong before the end. And then the error can be anything. Such a debug environment is not good where the error can be anything and waits until the end to generate error msg.
Altera_Forum
Honored Contributor
8 years ago
It wont show the error but as a warning when you are generating the qsys files than see on the box is it showing the warning as something like FWD_pointer.
Altera_Forum
Honored Contributor
8 years ago
Also can you attach the message files you are getting after building the project.
eamun1
New Contributor
4 years ago
Is this problem solved? I'm facing the same issue trying different quartus version. 19.1 18. 20.1

Forum Discussion

Downloading ELF failed

18 Replies

Recent Discussions

Part Status request

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy

Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger

IBIS models GTS banks agilex 5E