Download Option

The available configuration (download) options are discussed in the respective device manuals, you can also find schematics of most Altera and third party (e.g. Terasic) development kits as a reference at the vendors sites. To my opinion, a JTAG interface at the FPGA and an active serial configuration memory connected directly to the FPGA make the most simple design. The serial flash can be programmed through JTAG indirectly and don't need an individual programmer connection. With newer devices as Cyclone 3, a parallel flash may be an interesting alternative, but consuming more FPGA pins.