Honored Contributor
Honored ContributorI have found a solution to my own problem.
The issue seems to have been slow slew rate on the falling edge of the external oscillator signal. With a slow falling edge the voltage spends a relatively long time close to the threshold level of the relatively high speed input pin of the FPGA. In this sensitive crossing period, noise (in this case crosstalk) is able to toggle the threshold of the logic giving a very short pulse as a glitch with additional rising edge where only an isolated falling edge should have been. Given the speed of the Arria this glitch could easily be sub nanosecond in duration and therefore not visible to my oscilloscope probe when I brought the oscillator signal straight out on another pin of the FPGA. What I have done is remove some filtering I had on the oscillator output. This has had the effect of reduce the slew time from 2.1ns/V to 1.2ns/V. The faster edges now seem to be immune to the level of cross talk which had been affecting them and there are no more false triggers off the falling edge.
