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Altera_Forum's avatar
Altera_Forum
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11 years ago

Does the default HPS preloader/u-boot disable L1 and L2 cache?

Hi,

I am sharing the HPS DDR3 with a nios using the FPGA2SDRAM interface through and Address Span Extender (ASE). To boot Linux on the nios, u-boot running on the HPS follows these steps:

1. Copies (TFTP) the Linux binary image to the correct SDRAM address defined by the ASE.

2. Releases the reset for the nios.

This works fine but I am concerned that perhaps the whole image is not copied because the FPGA2SDRAM interface does not provide coherent SDRAM access with respect to the L1 and L2 caches of the MPU. I believe that the caches are probably disabled in u-boot in which case there should be no problem but i am not sure. Does anyone know?

I am using the u-boot this u-boot repository git://git.rocketboards.org/u-boot-socfpga.git where the socfpga_v2013.01.01-rel branch is checked out.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    This problem was solved through a service request with Altera so I just wanted to update the thread with the solution.

    U-boot does in fact enable the L1 data and instruction caches for the HPS. But I have confirmed that the data cache is set to writethrough mode. So anything copied by the HPS u-boot to shared memory is updated in full on the DDR and not stuck in the data cache.