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Altera_Forum's avatar
Altera_Forum
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11 years ago

Does the default HPS preloader/u-boot disable L1 and L2 cache?

Hi, I am sharing the HPS DDR3 with a nios using the FPGA2SDRAM interface through and Address Span Extender (ASE). To boot Linux on the nios, u-boot running on the HPS follows these steps: 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

This problem was solved through a service request with Altera so I just wanted to update the thread with the solution.

U-boot does in fact enable the L1 data and instruction caches for the HPS. But I have confirmed that the data cache is set to writethrough mode. So anything copied by the HPS u-boot to shared memory is updated in full on the DDR and not stuck in the data cache.