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Altera_Forum's avatar
Altera_Forum
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14 years ago

Does Altera provide the detail delay information for FPGA architecture?

Because I'm not sure whether Altera provides the information or not...

does anyone know where can I get the information?

The information is like the register input output capacitance, resistance, delay etc....for the architecture like ALM in Stratix II.

I'll be very appreciated with your help....

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    At least for the delays you should be able to get an idea as soon as you report & display pathes in the (time quest) timing analyzer. Just look at the time increase between an input and output of your desired device.

    Coming to resistance and capacitance I don't know, but I had never problems so far with the device, if timing was closed according to the timing analysis, so I did'nt care about...