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Altera_Forum's avatar
Altera_Forum
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10 years ago

Does a set_false_path constraint affect fitting or just ignores error?

Hello all,

I have made a design with one global clock coming from a PLL (150MHz).

Now i would like to slow down only one module of it using a different PLL output (100MHz). Data coming in and out of this module are updated much slower than the clocks.

So I have just created a pulse synchronizer to designate a data transfer between the two clock domains (module and rest of system) and the rest of the port interaction is left as it is using set_false_path constraints.

My question is:

If i put the set_false_path constraint in the sdc file, is it used during fitting? Will the set_false_path constraint affect the placing?

Also another question is, do I have to designate the pulse synchronizer, or is it automatically recognized?

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    setting false path (or defining clock groups) will remove burden of timing closure on relevant paths bridging clock domains and so affect routing. It also affects initial placement.

    If your clocks are 150 and 100 you may try assume them related first(i.e. no false path). if it fails then treat them as asynchronous. In this case you need just apply false path from one clock to the other or in both ways (if paths exists either way).

    Tools by default recognise synchroniser chains and report on MTBF on the path. check the compiler settings.