Forum Discussion
Altera_Forum
Honored Contributor
11 years agoDoes a set_false_path constraint affect fitting or just ignores error?
Hello all, I have made a design with one global clock coming from a PLL (150MHz). Now i would like to slow down only one module of it using a different PLL output (100MHz). Data coming in ...
Altera_Forum
Honored Contributor
11 years agosetting false path (or defining clock groups) will remove burden of timing closure on relevant paths bridging clock domains and so affect routing. It also affects initial placement.
If your clocks are 150 and 100 you may try assume them related first(i.e. no false path). if it fails then treat them as asynchronous. In this case you need just apply false path from one clock to the other or in both ways (if paths exists either way). Tools by default recognise synchroniser chains and report on MTBF on the path. check the compiler settings.