Documentation about resource usage of netlist cells

Dear Forum,

Xilinx has very good document - "Libraries Guide", about the netlist cells resource usage.

That document explains all standard cells used for synthesizing the design, and how many FPGA logic unit they are going to take after implementation.

This is the screenshot from that document:

http://www.alteraforum.com/forum/attachment.php?attachmentid=9755&stc=1

Do you know if Altera has similiar document?

Please help,

Thanks

Hayk