Documentation about resource usage of Altera cells

The Library Guide is definitely nice and Altera doesn't really have an equivalent. They tend to have designers build IP at a more general level, e.g. create a 2-Port RAM that is the size you want and let the tools build it out of the low-level primitives, rather than giving you a long list of primitives and having you manually stitch them together into what you want. I prefer that flow(and Xilinx allows it in many cases too with LogicCore), but there are times where occasionally you want the lowest level primitive that matches hardware to custom build something.