New ContributorDo any Intel FPGAs that set undefined values in registers after power up exist?
There is some discussions how to set default values or start an initial sequence in FPGAs design after programming/power-up.
- The most reliable method is using a supervisor IC which guaranteed send the reset signal. But this method needs a descrete IC on the board. Many boards haven't such supervisor.
- Less reliable method is usind a PLL lock signal for reset. But some small FPGAs (CPLDs) have not a PLL. The other counter argument is that if a PLL will fail for some clocks it cause not only skipping these clocks but the whole reinitializing of the FPGAs design.
- The other method is using some register with known default value to detect power-up condition and then changing this value. But if the registers default values are undefined this method did't work.
Do any Intel FPGAs that set undefined values in registers after power up exist?
Ok, so attached here are a couple of pages from an Altera Quartus manual that describe in detail this topic about registers.
Quoting:
"Registers in the device core always power up to a low (0) logic level on all Altera devices."
And a coding example of setting power up default value for a register:
Example 12-38: Verilog Register with High Power-Up Value reg q = 1’b1; //q has a default value of ‘1’ always @ (posedge clk) begin q <= d; end Example 12-39: VHDL Register with High Power-Up Level SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1' PROCESS (clk, reset) BEGIN IF (rising_edge(clk)) THEN q <= d; END IF; END PROCESS;
