Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

DMA controller memory verification failed

Hello , I have constructed a simple system to transfer data using DMA controller to initiate burst transfers from sdram to NIOS2 . The system is composed of onchip memory , sdram memory , sram me...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I'm a little surprised that you were able to set a maximum burst count higher than the FIFO depth. Also is there any particular reason why you have the burst count cranked way up to 512 beats? I don't know what kind of SDRAM you are using but I can assure you *no* memory out there needs such a large burst length to be efficient.