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Altera_Forum's avatar
Altera_Forum
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11 years ago

Distributing low frequency clock with Cyclone V FPGA

I am trying to use part of the Cyclone FPGA as a clock distribution chip. There is one input clock to FPGA (about 5 MHz), and I would like to distribute it into 4 outputs to four external chips.

The four outputs need to be exactly phase aligned, so the propagation delay from input pin to 4 output pins need to be exactly the same. Can I achieve the phase-aligned outputs by adding the maximum delay and minimum delay in SDC file?

My understanding is the Maximum delay and Minimum delay value should be very close to minimize the propagation delay differences. e.g.

# **************************************************************# Set Maximum Delay# **************************************************************

set_max_delay -from [get_ports {SYNC_OUT}] -to [get_ports {SYNC_IN_1 SYNC_IN_2 SYNC_IN_3 SYNC_IN_4}] 16.500

# **************************************************************# Set Minimum Delay# **************************************************************

set_min_delay -from [get_ports {SYNC_OUT}] -to [get_ports {SYNC_IN_1 SYNC_IN_2 SYNC_IN_3 SYNC_IN_4}] 16.400

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I would use the dedicated PLL's and their dedicated outputs for this task. The problem however, is only some of the PLL's have dedicated outputs.

    And they only have 2 outputs each.

    The timing will be much better since they will have dedicated routing. 5 MHz is the low end of the acceptable input clock frequency, so I would test do a test build to make sure the PLL's don't give you any surprises. The Cyclone V's also support a zero delay using external feedback, so that should improve your phase alingment.

    http://www.altera.com/literature/hb/cyclone-v/cv_52004.pdf

    describes the PLL's and their capabilities in more detail.

    Pete