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Altera_Forum
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11 years ago

Distributing low frequency clock with Cyclone V FPGA

I am trying to use part of the Cyclone FPGA as a clock distribution chip. There is one input clock to FPGA (about 5 MHz), and I would like to distribute it into 4 outputs to four external chips. ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

I would use the dedicated PLL's and their dedicated outputs for this task. The problem however, is only some of the PLL's have dedicated outputs.

And they only have 2 outputs each.

The timing will be much better since they will have dedicated routing. 5 MHz is the low end of the acceptable input clock frequency, so I would test do a test build to make sure the PLL's don't give you any surprises. The Cyclone V's also support a zero delay using external feedback, so that should improve your phase alingment.

http://www.altera.com/literature/hb/cyclone-v/cv_52004.pdf

describes the PLL's and their capabilities in more detail.

Pete