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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

DisplayPort IP generated design example supports ATX PLL ?

ATX PLL in the DisplayPort IP generated design example Hi, I have gone through the UG :Intel® Arria® 10 DisplayPort IP Core Design Example User Guide UG-20075...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Thanks for the clarification. I see your point now but this is not the recommended design practice.

  • It's recommended to always recalibration either the PLL or the transceiver channel depends you are modify which block to change speed
  • So that you get the most accurate internal analog setting tuned for your application current voltage and temperature condition


The pre-calibration feature in the DisplayPort example design is forced to be done to shorten the Displayport link boot time time. This is one outlier case here.


For your case, I suggest you to follow the recalibration process after changing speed as per guideline in Transceiver PHY user guide doc.


Thanks.


Regards,

dlim