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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Discuss the issue of PCIe

Hello everyone, I would like to discuss a problem related to PCIe transmission: I use stratix10 PCIe for avmm IP to transfer image data to CPU. The data is first written into DDR and then a frame of...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @allen18,


Thanks for reaching out to Intel Community Forum.


The situation you described could be a FIFO overflow situation. An FIFO overflow occurs when there's incoming data to write the full FIFO. In this case, you can try to increase the FIFO size (depth of the FIFO) to accommodate more data and overcome the overflow situation.


Thanks.

Best Regards,

VenTing_Intel