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Altera_Forum's avatar
Altera_Forum
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13 years ago

Digital division using Verilog

Hi.

I need to perform a division operation on a Cyclone IV FPGA.

I have learnt that the few methods to perform such are :

(a) by calling the conventional '/' operator; eg 27/5

(b) by calling megafunction altfp_div or lpm_div

(c) by performing multiplication to the inverse of the numerator.

I have first performed (a), which then I found out that it has utilized too much of resources.

and I have learnt that the '/' operation could not be synthesized in Verilog as well.

I am now using lpm_div to perform my (fixed point) divisions.

My question is, when I view the compilation report, it shows that this megafunction does not use any of the LE nor embedded memory. (The inputs to my lpm_div module are constants.)

May I know how is this possible?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Because the inputs to your module are constants, Quartus might be pre-calculating the result and using the new constant instead of the device resources.

    Another resource to keep an eye on are DSP elements. (multiply blocks)

    If you have the clocks to spare, you may consider performing a subtraction routine to achieve your division.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    kosh is correct, with constant inputs Quartus will just plug in the answer instead of instantiating hardware for the division (just like software compilers would).

    If you want to experiment with different implementations and want a somewhat accurate logic count I would assign the inputs and outputs to virtual pins.

    Depending on what you are attempting lpm_div might be overkill. Do you have bounds on your inputs (assuming they aren't constant... otherwise there is no point using lpm_div). For example a narrow division by constant can be replaced with a lookup table. Or if you are performing a wide division by constant you can replace that with shifts and adds. If you don't care about pipelining the results you can also go with a serial divider (implemented as long division). So there are lots of alternatives but most of them require you to determine the bounds of the problem you are trying to solve.