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Altera_Forum
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13 years ago

Digital division using Verilog

Hi. I need to perform a division operation on a Cyclone IV FPGA. I have learnt that the few methods to perform such are : (a) by calling the conventional '/' operator; eg 27/5 (b) by cal...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Because the inputs to your module are constants, Quartus might be pre-calculating the result and using the new constant instead of the device resources.

Another resource to keep an eye on are DSP elements. (multiply blocks)

If you have the clocks to spare, you may consider performing a subtraction routine to achieve your division.