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Altera_Forum's avatar
Altera_Forum
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11 years ago

Digital audio player, help choosing the right device

I'm not sure this is the right forum section to post the new thread.

I'm new in FPGA design, so I need some suggestions to choise the right device.

I would build a digital audio player with the following characteristics:

- it should read data from SD card only

- SD card will be formatted FAT32

- the root of SD card will contain folders only (named as album title/artist)

- no subfolders will be allowed on SD card

- each SD card folder will contain wav files only (named as title track)

- only 16 bit / 44.1 kHz wav files will be allowed (CD quality)

- music data should be read and managed synchronously

- 7 buttons have to be managed: previous track, next track, play, stop, pause, return and enter to navigate the folders

- LCD display will be managed to show album/artist, title track, time elapsed and so on

- data output (16 bit serial X 2 channels) should feed a r-2r discrete ladder DAC

- 74XX595 logic will split the serial data to parallel to feed the ladder network

- master clock should be 11.2896 MHz, shared from both DAC logic and FPGA/ARM, to avoid any divider

- every time a single bit is ready, FPGA should enable the 595 to store it (595 clock enabled from FPGA in sync with master clock)

- every time 16 bit for 2 channels are read, FPGA in sync with master clock should enable the 595s to output parallel data to update the ladder network

Practically, file system and wav headers aside, using 11.2896 MHz master clock for all the system, I have to start reading 4 bytes from the SD

card (1 left + 1 right samples), then I should pass each single bit synchronously to 4 * 74XX595.

The clock of the 595 to store data should be enabled either from the master clock and the FPGA (data ready to store).

After the 32th bit is stored in the last 595, FPGA should enable the master clock to tell all the 595s to output parallel data to update the ladder network.

Finally the clock of all the 595s should be stopped for 224 cycles, and no data should be read from the SD card.

Now the program has to read next 4 bytes, until the end of the wav file.

In the meantime I have to manage the LCD display and interrupt from the user buttons.

What device do you suggest to do all the above job? FPGA, CPLD or FPGA with ARM embedded?

Can I run all the system at the same master clock (11.2896 MHz)?

Can I read and manage data synchronously from the SD card?

Thanks

Andrea

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Ehm, it's kinda awkward to say this on an Altera forum, but it doesn't look like you need an FPGA here. Reading a FAT filesystem means that you probably need a decent processor (most likely some ARM, but there are other around). Audio is something commonly supported. You can, of course, do this with an FPGA or a SoC device, but it's a heavy overkill, and odds are that a plain processor device will be the most cost-effective.

    Cheers,

    Andrew
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Ehm, it's kinda awkward to say this on an Altera forum, but it doesn't look like you need an FPGA here. Reading a FAT filesystem means that you probably need a decent processor (most likely some ARM, but there are other around). Audio is something commonly supported. You can, of course, do this with an FPGA or a SoC device, but it's a heavy overkill, and odds are that a plain processor device will be the most cost-effective.

    Cheers,

    Andrew

    --- Quote End ---

    Sorry for my ignorance, do you think I can use also a Cyclone V SE with ARM embedded?

    Or a Cyclone V GX with Nios processor?

    There are 2 examples in the evaluation board user manual (C5G_User_Manual.pdf from Terasic):

    - 6.6 Micro SD Card file system read

    - 6.7 SD Card music player demonstration

    Andrea
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Like Andrew said, there's really no reason to go with an FPGA here and you'll end up overcomplicating things on a massive scale. While you could go the whole SoC route, you'll end up mostly writing C/C++ code to do what you want it to do. Take an off-the-shelf part and add a few parts to it and save yourself the headache.

    -Mux

    Edit: You could even do this with a decent micro-controller.