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Altera_Forum
Honored Contributor
12 years agoI solved this, the reason is timing error (slack too much) :
1. Use afi_clk to drive both h2f axi master and the fifos 2. Use higher frequency on fpga_clk_50 to 125mhzI solved this, the reason is timing error (slack too much) :
1. Use afi_clk to drive both h2f axi master and the fifos 2. Use higher frequency on fpga_clk_50 to 125mhz