In addition to jtag, which is normally used only in the design/debug stage, FPGAs are configured with device specific methods; these are described in the datasheet. For Altera FPGAs the configuration can be AS (active serial), PS passive serial) or FPP (fast passive parallel) and the programming device is an external eprom, a microprocessor or else.
Ethernet, USB, PCI and so on can be used, but you need an interface device (i.e a microprocessor or a pld) to properly receive data and feed it to fpga.
For example, when the host processor receives FPGA configuration from USB, it resets FPGA in the PS mode and programs the received data by means of a spi port
If you can't afford adding a microprocessor, you must configure through a flash eprom (i.e. active serial mode) and rely on remote update feature. FPGA can be configured to manage the Ethernet/USB/... protocol itself. Please note that the FPGA has not a native interface to these protocols, so you need to use a lot of resources to implement; then, this solution is convenient and widely used if your design is supposed to use the same interface for normal operation, not only for configuration or remote update
Regards
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