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Altera_Forum's avatar
Altera_Forum
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13 years ago

Different results on hardware compared to simulator

I'm having trouble when I run my code on the actual Cyclone III FPGA. In the simulator it works fine. I have set up state machines to make sure that clock signals to registers are occurring after ple...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

As I said before the safest method is one clock system with various rate control adjusted through clk enable. If you have to use more than one clk then you need to cross clk domains which is tricky for a beginner.